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ADC0801S040 single 8 bits adc, up to 40 mhz rev. 03 ? 2 july 2012 product data sheet 1. general description the ADC0801S040 is an 8-bit universal analog-to-digital converter (adc) for video and general purpose applications. it converts the analog input signal from 2.7 v to 5.5 v into 8-bit binary-coded digital words at a maximum sampling rate of 40 mhz. all digital inputs and outputs are cmos/transistor-transistor logic (ttl) compatible. a sleep mode allows reduction of the devic e power consumption to 4 mw. 2. features ? 8-bit resolution ? oper ation between 2.7 v and 5.5 v ? sa mpling rate up to 40 mhz ? dc sampling allowed ? high signal-to-noise ratio over a large analog input frequency range (7.3 effective bits at 4.43 mhz full-scale input at f clk = 40 mhz) ? cmos/tt l compatible digital inputs and outputs ? exte rnal reference voltage regulator ? power dissip ation only 30 mw (typical value) ? l ow analog input capacitance, no buffer amplifier required ? slee p mode (4 mw) ? no samp le-and-hold circuit required 3. applications ? video data digitizing ? came ra ? camcorder ? rad io communication ? car alarm system
3ADC0801S040_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 2 of 18 integrated device technology ADC0801S040 single 8 bits adc, up to 40 mhz 4. quick reference data table 1. quick reference data v dda = v5 to v6 = 3.3 v; v ddd = v3 to v4 = 3.3 v; v ddo = v20 to v11 = 3.3 v; v ssa , v ssd and v sso shorted together; v i(a)(p-p) = 1.84 v; c l = 20 pf; t amb = 0 ? c to 70 ? c; typical values measured at t amb = 25 ? c unless otherwise specified. symbol parameter conditions min typ max unit v dda analog supply voltage 2.7 3.3 5.5 v v ddd digital supply voltage 2.7 3.3 5.5 v v ddo output supply voltage 2.5 3.3 5.5 v ? v dd supply voltage difference v dda ? v ddd ? 0.2 - +0.2 v v ddd ? v ddo ? 0.2 - +2.25 v i dda analog supply current - 4 6 ma i ddd digital supply current - 5 8 ma i ddo output supply current f clk = 40 mhz; ramp input; c l = 20 pf - 1 2 ma inl integral n on-linearity ramp input; see figure 6 - ? 0.5 ? 0.75 lsb dnl differential n on-linearity ramp input; see figure 7 - ? 0.25 ? 0.5 lsb f clk(max) maximum clock frequency 40 - - mhz p tot total power dissipation v dda = v ddd = v ddo = 3.3 v - 30 53 mw 5. ordering information table 2. ordering information type number package name description version ADC0801S040ts ssop20 plastic shrink small outline package; 20 leads; body width 4.4 mm sot266-1
3ADC0801S040_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 3 of 18 integrated device technology ADC0801S040 single 8 bits adc, up to 40 mhz 6. block diagram 7 9 r lad 8 10 rb rm rt vi 3 v ddd 5 v dda 2 cmos outputs latches clock driver 014aaa495 1 clk sleep ADC0801S040 20 v ddo 6 v ssa analog ground digital ground 4 v ssd 11 v sso output ground analog voltage input data outputs lsb msb 19 d7 18 d6 17 d5 16 d4 15 d3 14 d2 13 d1 12 d0 analog - to - digital converter fig 1. block diagram
3ADC0801S040_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 4 of 18 integrated device technology ADC0801S040 single 8 bits adc, up to 40 mhz 7. pinning information 7.1 pinning adc0801s 040ts clk v ddo sleep d7 v ddd d6 v ssd d5 v dda d4 v ssa d3 rb d2 rm d1 vi d0 rt v sso 014aaa494 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 fig 2. pin configuration 7.2 pin description table 3. pin description symbol pin description clk 1 clock input sleep 2 sleep mode input v ddd 3 digital supply voltage (2.7 v to 5.5 v) v ssd 4 digital ground v dda 5 analog supply voltage (2.7 v to 5.5 v) v ssa 6 analog ground rb 7 reference voltage bottom input rm 8 reference voltage middle vi 9 analog input voltage rt 10 reference voltage top input v sso 11 output stage ground d0 12 data output; bit 0 (least significant bit (lsb)) d1 13 data output; bit 1 d2 14 data output; bit 2 d3 15 data output; bit 3 d4 16 data output; bit 4 d5 17 data output; bit 5
3ADC0801S040_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 5 of 18 integrated device technology ADC0801S040 single 8 bits adc, up to 40 mhz 8. limiting values table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dda analog supply voltage [1] ? 0.3 +7.0 v v ddd digital supply voltage [1] ? 0.3 +7.0 v v ddo output supply voltage [1] ? 0.3 +7.0 v ? v dd supply voltage difference v dda ? v ddd ; v ddd ? v ddo ; v dda ? v ddo ? 0.1 +4.0 v v i input voltage referenced to v ssa ? 0.3 +7.0 v v i(clk)(p-p) peak-to-peak clock input voltage referenced to v ssd - v ddd v i o output current - 10 ma t stg storage temperature ? 55 +150 ?c t amb ambient temperature ? 20 +75 ?c t j junction temperature - 150 ?c [1] the supply voltages v dda , v ddd and v ddo may have any value between ? 0.3 v and +7.0 v provided that the supply voltage ? v dd remains as indicated. 9. thermal characteristics table 5. thermal characteristics symbol parameter condition value unit r th(j-a) thermal resistance from junction to ambient in free air 120 k/w 10. characteristics d6 18 data output; bit 6 d7 19 data output; bit 7 (most significant bit (msb)) v ddo 20 positive supply voltage for output stage (2.7 v to 5.5 v) table 3. pin description ?continued symbol pin description table 6. characteristics v dda = v5 to v6 = 3.3 v; v ddd = v3 to v4 = 3.3 v; v ddo = v20 to v11 = 3.3 v; v ssa , v ssd and v sso shorted together; v i(a)(p-p) = 1.84 v; c l = 20 pf; t amb = 0 ? c to 70 ? c; typical values measured at t amb = 25 ? c unless otherwise specified. symbol parameter conditions min typ max unit supplies v dda analog supply voltage 2.7 3.3 5.5 v v ddd digital supply voltage 2.7 3.3 5.5 v v ddo output supply voltage 2.5 3.3 5.5
3ADC0801S040_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 6 of 18 integrated device technology ADC0801S040 single 8 bits adc, up to 40 mhz ' v dd supply voltage difference v dda v ddd 0.2 - +0.2 v v ddd v ddo 0.2 - +2.25 v i dda analog supply current - 4 6 ma i ddd digital supply current - 5 8 ma i ddo output supply current f clk = 40 mhz; ramp input; c l = 20 pf - 1 2 ma p tot total power dissipation v dda = v ddd = v ddo = 3.3 v - 30 53 mw inputs clock input clk (referenced to v ssd ) [1] v il low-level input voltage 0 - 0.3 v ddd v v ih high-level input voltage v ddd d 3.6 v 0.6 v ddd - v ddd v v ddd > 3.6 v 0.7 v ddd - v ddd v i il low-level input current v clk = 0.3 v ddd 1 0 +1 p a i ih high-level input current v clk = 0.7 v ddd - - 5 p a z i input impedance f clk = 40 mhz - 4 - k : c i input capacitance f clk = 40 mhz - 3 - pf input sleep (referenced to v ssd ); see table 8 v il low-level input voltage 0 - 0.3 v ddd v v ih high-level input voltage v ddd d 3.6 v 0.6 v ddd - v ddd v v ddd > 3.6 v 0.7 v ddd - v ddd v i il low-level input current v il = 0.3 v ddd 1 - - p a i ih high-level input current v ih = 0.7 v ddd - - +1 p a analog input vi (referenced to v ssa ) i il low-level input current v i = v rb - 0 - p a i ih high-level input current v i = v rt - 9 - p a z i input impedance f i = 1 mhz - 20 - k : c i input capacitance f i = 1 mhz - 2 - pf reference voltages for the resistor ladder; see table 7 v rb voltage on pin rb 1.1 1.2 - v v rt voltage on pin rt v rt d v dda 2.7 3.3 v dda v v ref(dif) differential reference voltage v rt v rb 1.5 2.1 2.7 v i ref reference current - 0.95 - ma r lad ladder resistance - 2.2 - k : tc rlad ladder resistor temperature coefficient - 4092 - m : /k v offset offset voltage bottom [2] - 170 - mv top [2] - 170 - mv v i(a)(p-p) peak-to-peak analog input voltage [3] 1.4 1.76 2.4 v table 6. characteristics ?continued v dda = v5 to v6 = 3.3 v; v ddd = v3 to v4 = 3.3 v; v ddo = v20 to v11 = 3.3 v; v ssa , v ssd and v sso shorted together; v i(a)(p-p) = 1.84 v; c l = 20 pf; t amb = 0 q c to 70 q c; typical values measured at t amb = 25 q c unless otherwise specified. symbol parameter conditions min typ max unit
3ADC0801S040_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 7 of 18 integrated device technology ADC0801S040 single 8 bits adc, up to 40 mhz digital outputs d7 to d0 and ir (referenced to v ssd ) v ol low-level output voltage i o = 1 ma 0 - 0.5 v v oh high-level output voltage i o = 1 ma v ddo 0.5 - v ddo v i oz off-state output current 0.4 v < v o < v ddo 20 - +20 p a clock input clk; see figure 4 [1] f clk(max) maximum clock frequency 40 - - mhz t w(clk)h high clock pulse width 9 - - ns t w(clk)l low clock pulse width 9 - - ns analog signal processing (f clk = 40 mhz) linearity inl integral non-linearity ramp input; see figure 6 - r 0.5 r 0.75 lsb dnl differential non-linearity ramp input; see figure 7 - r 0.25 r 0.5 lsb bandwidth b bandwidth full-scale sine wave [4] - 10 mhz 75 % full-scale sine wave - 13 mhz 50 % full-scale sine wave - 20 mhz small signal at mid scale; v i = r 10 lsb at code 128 - 350 mhz input set response; see figure 8 [5] t s(lh) low to high settling time full-scale square wave - 3 5 ns t s(hl) high to low settling time full-scale square wave - 3 5 ns harmonics; see figure 9 [6] thd total harmonic distortion f i = 4.43 mhz - 50 - db signal-to-noise ratio; see figure 9 [6] s/n signal-to-noise ratio without harmonics; f i = 4.43 mhz - 47 - db effective bits; see figure 9 [6] enob effective number of bits f i = 300 mhz - 7.8 - bits f i = 4.43 mhz - 7.3 - bits differential gain [7] g dif differential gain pal modulated ramp - 1.5 - % table 6. characteristics ?continued v dda = v5 to v6 = 3.3 v; v ddd = v3 to v4 = 3.3 v; v ddo = v20 to v11 = 3.3 v; v ssa , v ssd and v sso shorted together; v i(a)(p-p) = 1.84 v; c l = 20 pf; t amb = 0 q c to 70 q c; typical values measured at t amb = 25 q c unless otherwise specified. symbol parameter conditions min typ max unit
3ADC0801S040_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 8 of 18 integrated device technology ADC0801S040 single 8 bits adc, up to 40 mhz [1] in addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 1 ns. [2] analog input voltages producing code 0 up to and including code 255: a) v offset bottom is the difference between the analog input which produces data equal to 00 and the reference voltage on pin rb (v rb ) at t amb = 25 ? c. b) v offset top is the difference between the reference voltage on pin rt (v rt ) and the analog input which produces data outputs equal to code 255 at t amb = 25 ? c . [3] to ensure the optimum linearity performance of such a converte r architecture the lower and upper extremities of the converte r reference resistor ladder are connected to pins rb and rt via offset resistors r ob and r ot as shown in figure 3. a) the current flowing into the resistor ladder is i v rt v rb ? r ob r l r ot ++ --------------------------------------- = and the full-scale input range at the converter, to cover code 0 to 255 is v i r l i l ? r l r ob r l r ot ++ --------------------------------------- v rt v rb + ?? ? 0.838 v rt v rb ? ?? ? == = b) since r l , r ob and r ot have similar behavior with respect to process and temperature variation, the ratio r l r ob r l r ot ++ --------------------------------------- will be kept reasonably constant from devic e to device. consequen tly variation of the output codes at a given input voltage dep ends mainly on the difference v rt ? v rb and its variation with temperature and supply voltage. when several adcs are connected in parallel and fed with the same reference source, the matching between each of them is optimized. [4] the analog bandwidth is defined as the maximum input sine wave fre quency which can be applied to the device. no glitches gre ater than 2 lsb, nor any significant attenuation is observed in the reconstructed signal. [5] the analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale i nput (square wave signal) in order to sample the signal and obtain correct output data. [6] effective bits are obtained via a fast fourier transform (f f t) treatment taking 8000 acquisition points per equivalent funda mental period. the calculation takes into account all harmonics and noise up to half of the clock frequency (nyquist frequency). conve rsion to signal-to-noise ratio: s/n = enob ? 6.02 + 1.76 db. [7] measurement carried out using video analyzer vm700a, wher e video analog signal is r econstructed through a dac. [8] output data acquisition: the output data is available af ter the maximum delay time of t d(o) . differential phase [7] ? dif differential phase pal modulated ramp - 0.25 - deg timing (f clk = 40 mhz; c l = 20 pf); see figure 4 [8] t d(s) sampling delay time - - 5 ns t h(o) output hold time 5 - - ns t d(o) output delay time v ddo = 4.75 v 8 12 15 ns v ddo = 3.15 v 8 17 20 ns v ddo = 2.7 v 8 18 21 ns 3-state output delay times; see figure 5 t dhz active high to float delay time - 14 18 ns t dzl float to active low delay time - 16 20 ns t dzh float to active high delay time - 16 20 ns t dlz active low to float delay time - 14 18 ns table 6. characteristics ?continued v dda = v5 to v6 = 3.3 v; v ddd = v3 to v4 = 3.3 v; v ddo = v20 to v11 = 3.3 v; v ssa , v ssd and v sso shorted together; v i(a)(p-p) = 1.84 v; c l = 20 pf; t amb = 0 ? ? ? symbol parameter conditions min typ max unit
3ADC0801S040_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 9 of 18 integrated device technology ADC0801S040 single 8 bits adc, up to 40 mhz 014aaa504 rt rb rm r lad r ot r l r l r l r l i l r ob code 255 code 0 9 7 6 fig 3. explanation of table 6 table note 3 11. additional information relating to table 6 table 7. output coding and input voltage (typical values; referenced to v ssa ) code v i(a)(p-p) (v) binary outputs d7 to d0 underflow < 1.37 00 0000 00 0 1.37 00 0000 00 1 - 00 0000 01 ? - ? 254 - 11 11 11 10 255 3.13 11 11 11 11 overflow > 3.13 11 11 11 11 table 8. mode selection sleep d7 to d0 i dda + i ddd (typ) 1 high impedance 1.2 ma 0 active 9 ma
3ADC0801S040_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 10 of 18 integrated device technology ADC0801S040 single 8 bits adc, up to 40 mhz sample n + 1 sample n clk 014aaa508 sample n + 2 sample n + 1 sample n sample n + 2 50 % vi data d0 to d7 v ddo 0 v 50 % data n + 1 data n data n ? 1 data n ? 2 t d(o) t w(clk)h t w(clk)l t d(s) t h(o) fig 4. timing diagram
3ADC0801S040_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 11 of 18 integrated device technology ADC0801S040 single 8 bits adc, up to 40 mhz low high high low ADC0801S040 v ddd v ddd s1 sleep sleep output data output data 10 % 50 % 50 % 90 % 50 % t dlz t dzl t dhz t dzh 20 pf 3.3 k s1 test v ddd t dlz v ddd t dzl gnd t dzh t dhz gnd 014aaa496 frequency on pin sleep = 100 khz. fig 5. timing diagram and test condit ions of 3-state output delay time 014aaa501 ?0.047 0.065 ?0.160 0.178 0.291 a (lsb) ?0.272 codes 0 272 204 68 136 fig 6. typical integral non-linearity (inl) performance
3ADC0801S040_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 12 of 18 integrated device technology ADC0801S040 single 8 bits adc, up to 40 mhz 014aaa502 ?0.025 0.032 ?0.84 0.091 0.150 a (lsb) ?0.143 codes 0 272 204 68 136 fig 7. typical differential non-linearity (dnl) performance 014aaa497 code 255 code 0 50 % 50 % clk vi t s(lh) t s(hl) 50 % 50 % 5 ns 5 ns 2 ns 2 ns fig 8. analog input se ttling-time diagram
3ADC0801S040_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 13 of 18 integrated device technology ADC0801S040 single 8 bits adc, up to 40 mhz f (mhz) 0 20.0 15.0 5.0 10.0 014aaa503 ?80 ?40 0 a (db) ?120 effective bits: 7.32; thd = ?51.08 db. harmonic levels (db): 2nd = ?68.9 9; 3rd = ? 51.62; 4th = ? 66.05; 5th = ? 63.23; 6th = ?72.79. fig 9. typical fast fourier transform (f clk = 40 mhz; f i = 4.43 mhz) 014aaa498 v ddo d7 to d0 v sso v dda vi v ssa 014aaa505 fig 10. cmos data outputs fig 11. vi analog input 014aaa499 v ddo v sso sleep v dda rt rm rb v ssa 014aaa506 r l r l r l r l fig 12. sleep 3-state input fig 13. rb, rm and rt inputs
3ADC0801S040_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 14 of 18 integrated device technology ADC0801S040 single 8 bits adc, up to 40 mhz v ddd clk 1 / 2 v ddd v ssd 014aaa507 fig 14. clk input
3ADC0801S040_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 15 of 18 integrated device technology ADC0801S040 single 8 bits adc, up to 40 mhz 12. application information 12.1 application diagrams 100 nf 100 nf 100 nf clk sleep v ddd v ssd v dda v ssa v ssa v ssa v ssa rb(1) rm(1) vi rt(1) v ddo d7 d6 d5 d4 d3 d2 d1 d0 v sso 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 ADC0801S040 014aaa500 the analog and digital supplies should be separated and decoupled. the external voltage reference generator must be built in such a way that a good supply voltage ripple rejection is achieved with respect to the lsb value. eventually, the reference ladder voltages can be derived from a well regulated v dda supply through a resistor bridge and a decoupling capacitor. (1) rb, rm, rt are decoupled to v ssa . fig 15. application diagram
3ADC0801S040_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 16 of 18 integrated device technology ADC0801S040 single 8 bits adc, up to 40 mhz 13. package outline unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0 1.4 1.2 0.32 0.20 0.20 0.13 6.6 6.4 4.5 4.3 0.65 1 0.2 6.6 6.2 0.65 0.45 0.48 0.18 10 0 o o 0.13 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.20 mm maximum per side are not included. 0.75 0.45 sot266-1 mo-152 99-12-27 03-02-19 w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a x (a ) 3 a y 0.25 11 0 20 11 pin 1 index 0 2.5 5 mm scale ssop20: plastic shrink small outline package; 20 leads; body width 4.4 mm sot266-1 a max. 1.5 fig 16. package outline sot266-1 (ssop20)
3ADC0801S040_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 17 of 18 integrated device technology ADC0801S040 single 8 bits adc, up to 40 mhz 14. revision history table 9. revision history document id release date data sheet status change notice supersedes ADC0801S040_3 20120702 product data sheet - ADC0801S040_2 ADC0801S040_2 20080818 product data sheet - ADC0801S040_1 modifications: corrections made to table notes in figure ? 1. corrections made to table ? 3. corrections made to symbol in table ? 4. corrections made to table ? 6. corrections made to figure ? 13 ADC0801S040_1 20080612 product data sheet - - 15. contact information for more information or sales office addresses, please visit: http://www.idt.com
3ADC0801S040_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 18 of 18 integrated device technology ADC0801S040 single 8 bits adc, up to 40 mhz 16. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 thermal characteristics . . . . . . . . . . . . . . . . . . 5 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 5 11 additional informa tion relating to table 6 . . . 9 12 application information . . . . . . . . . . . . . . . . . 15 12.1 application diagrams . . . . . . . . . . . . . . . . . . . 15 13 package outline. . . . . . . . . . . . . . . . . . . . . . . . 16 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 17 15 contact information . . . . . . . . . . . . . . . . . . . . 17 16 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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